1. Field of the Invention
The present invention relates to an information processing apparatus including a wide IO memory device stacked on an SoC die that includes a CPU.
2. Description of the Related Art
In information processing apparatuses that include a CPU such as a microprocessor, a DRAM is often used for storage of data for executing an OS and various applications, and for temporary storage of data for executing image processing. The DRAM is connected to a CPU, an SoC (System on a Chip), or the like and used by them. Furthermore, in recent years, as functions have been added/enhanced in information processing apparatuses, the amount of memory bandwidth needed in DRAMs has increased. Because of this, the amount of memory bandwidth has been increased by raising the clock frequency during memory access, according to a standard such as DDR3 or DDR4. Furthermore, as another method, memory bandwidth is reserved by including multiple DRAM channels that are connected to a CPU or an ASIC (Application Specific Integrated Circuit). However, a new problem occurs in that increasing the clock frequency and employing multiple memory channels increases power consumption.
In view of this, wide IOs, which are a next-generation DRAM standard, are currently gaining attention. A wide IO is configured by placing a DRAM chip over an SoC die using a 3D stacking technique based on TSVs (Through-Silicon Vias). Features of the wide IO include being able to obtain a wide bandwidth that is over 12.8 GB/s (gigabytes per second) at most, with a wide data width of 512 bits, and having low power consumption due to the access frequency being suppressed to a low frequency. Also, by employing TSVs, the package size can be made thinner and smaller compared to a conventional PoP (Package on Package). Furthermore, as a countermeasure against heat caused by stacking memories in an SoC package, a temperature sensor that detects the memory temperature is built in, and the self-refresh rate is changed according to the detected temperature. Also, in this configuration, a data width of 512 bits is divided into four 128-bit channels and each channel is controlled individually. For example, a method of use is possible in which channel 1 and channel 2 are put in a self-refresh state, while channel 3 and channel 4 are used for normal memory access, or the like. A basic structure and basic access method for such a wide IO is disclosed in US Patent Application Publication No. 2012/0018885.
The stacked structure of a wide IO is structurally susceptible to heat. For example, if a specific region of a SoC die and a DRAM chip of a wide IO placed on a layer above this specific region are activated at the same time, the temperature of the activated portions sometimes rises locally. This rise in temperature is accompanied by an exponential increase in leak current in the semiconductor and an increase in power consumption.
In view of this, the DRAM performs storage of data by storing charge in a capacitor included in each cell. Since the capacitors are naturally discharged by leak current in the semiconductor, it is necessary for the DRAM to charge the capacitors by performing a refresh operation, in order to preserve the stored data. The discharging of this charge depends on the temperature of the DRAM, and the higher the temperature is, the faster the discharge speed is. Accordingly, if the temperature of the DRAM becomes high, the refresh frequency needs to be increased. As a result, this invites an increase in power consumption caused by refresh operations, as well as the deterioration of the access performance of the DRAM due to not being able to access the DRAM during a refresh operation.
Additionally, the amount of heat generated in the circuits is generally proportional to the power consumption of the circuits. If a wide IO DRAM, which is susceptible to heat, is used as a memory device, it is necessary to address increases in power consumption in order to suppress the amount of heat generated in the circuits more than in the case of using another memory device.
In view of this, it is envisioned that power consumption will be further reduced with a wide IO by, using the feature of being able to control memory channels individually, actively controlling the memory channels not only when operating in a power-saving mode, but also when operating in a normal operation mode. For example, control to operate, in standby mode, a wide IO DRAM in a power-saving mode such as a self-refresh mode, and to cause, when the execution of certain processing is needed, only a needed memory channel to return from the power-saving mode is envisioned.
When subjecting a wide IO DRAM to this kind of control, it is necessary to further lower the operation frequency of the DRAM in order to achieve greater power conservation. However, if the operation frequency is simply reduced, there is a problem in that the memory bandwidth decreases and the access performance of the DRAM deteriorates. Due to this deterioration of DRAM access performance, the performance of the system that includes the SoC package deteriorates, and the product performance deteriorates.